In the field of frequency generation, frequency dividers may be used to divide the frequency of the clock of a controlled oscillator (CO). The divided clock output of the divider may then be input to a phase detector for comparison with a reference clock. The output of the phase detector may be used to control the CO until the divided clock and the reference clock are frequency locked. In this configuration, the output CO frequency (Fo) may be equal to the reference clock frequency (Fr) multiplied by the divider factor N: Fo=N*Fr. For standard frequency dividers, N may be bounded to be an integer value, so that Fo is an integer multiple of Fr.
For applications including generation of carrier frequency for channels in wireless applications, generation of spread-spectrum clocks in wireline applications, and generation of multiple frequencies from a common CO in general clock generation units, it may be desirable for Fo to be a fractional multiple of Fr, so that N may be a fractional number.